It is frequently desired in the microelectronics industry to use only a single voltage (e.g., five volt) external power supply to supply all the power needs for a microcircuit. It is further desirable to fabricate on-chip voltage multiplier circuits to provide a voltage which is higher than the external power supply voltage to drive, for example, a gate of an NMOS transistor for higher output current throughput or to provide high erase and write voltages for electrically erasable programmable read-only memories (EEPROMs).
FIG. 1 is a schematic diagram of a representative voltage doubler which may be implemented in an integrated circuit. Voltage doubler 10 of FIG. 1 uses the voltage across two series connected capacitors C1 and C2 as its output. The remainder of the voltage doubler 10 circuitry acts to charge each capacitor C1 and C2 individually to the supply voltage V.sub.cc when square wave signals 12 and 14, 180.degree. out-of-phase with each other and both with an amplitude of supply voltage V.sub.cc, are applied to the input terminals of voltage doubler 10. Thus, each of the two signals 12 and 14 charge respective capacitors C1 and C2 to the peak supply voltage V.sub.cc of, for example, five volts so that the voltage across the series connected capacitors C1 and C2 is roughly twice that of the amplitude of signals 12 and 14--in this case, ten volts. If a voltage tripler was desired, three out-of-phase signals would be required to charge up three series connected capacitors to the power supply voltage to produce roughly triple the power supply voltage across the capacitors.
Prior art voltage multiplier structures form each of the capacitors by providing a highly conductive polysilicon layer over, and insulated from, a highly conductive diffused region, as shown in FIG. 2. In FIG. 2, polysilicon layers 20 and 22 act as upper plates of capacitors C1 and C2 while diffused regions 24 and 26 act as bottom plates of the capacitors. Electrodes 28, 30, 32, and 34 provide the proper coupling to the diffused regions and the polysilicon upper plates. As greater voltage multiplication is desired, more and more capacitors are required, resulting in more real estate being used to accommodate the necessary number of capacitors. Further, each individual capacitor is affected by a parasitic capacitance between the diffused region and the substrate.
In Japanese Patent No. 59-89450 to Miyamoto, a multilayer capacitor of a large capacitance is shown in which a diffused region in a substrate forms a lower plate of a first capacitor. An insulating layer is formed over this diffused region and a first polysilicon layer is formed thereon, forming an upper plate of the first capacitor and an upper plate of a second capacitor. A second polysilicon layer is formed over and insulated from the first polysilicon layer to form a lower plate of the second capacitor and a lower plate of a third capacitor. A third polysilicon layer is formed over and insulated from the second polysilicon layer to form the upper plate of the third capacitor and an upper plate of a fourth capacitor. A fourth polysilicon layer forms the lower plate of the fourth capacitor. The diffused region, the second polysilicon layer, and the fourth polysilicon layer are coupled together via a first electrode, and the first polysilicon layer and the third polysilicon layer are coupled together with a second electrode. This arrangement in Miyamoto results in the equivalent of four capacitors connected in parallel, wherein the resulting large capacitor has only two terminals for connection to other circuitry. This type of capacitor cannot be used in a voltage multiplier circuit to form capacitors C1 and C2 in FIG. 1 since capacitors C1 and C2 must be in series.
No prior art voltage multiplier has utilized multiple polysilicon layers in the formation of serial capacitances, and further, no prior art has been found which discloses multiple polysilicon layers in the formation of individual discrete capacitors which are in a stacked structure.